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 temporally asymmetric hebbian learning


Temporally Asymmetric Hebbian Learning, Spike liming and Neural Response Variability

Neural Information Processing Systems

Recent experimental data indicate that the strengthening or weakening of synaptic connections between neurons depends on the relative timing of pre- and postsynaptic action potentials. A Hebbian synaptic modification rule based on these data leads to a stable state in which the excitatory and inhibitory inputs to a neuron are balanced, producing an irregular pattern of firing. It has been proposed that neurons in vivo operate in such a mode.


Citcuits for VLSI Implementation of Temporally Asymmetric Hebbian Learning

Neural Information Processing Systems

Experimental data has shown that synaptic strength modification in some types of biological neurons depends upon precise spike tim(cid:173) ing differences between presynaptic and postsynaptic spikes. Sev(cid:173) eral temporally-asymmetric Hebbian learning rules motivated by this data have been proposed. We argue that such learning rules are suitable to analog VLSI implementation. We describe an eas(cid:173) ily tunable circuit to modify the weight of a silicon spiking neuron according to those learning rules. Test results from the fabrication of the circuit using a O.6J.lm CMOS process are given.


Citcuits for VLSI Implementation of Temporally Asymmetric Hebbian Learning

Neural Information Processing Systems

Experimental data has shown that synaptic strength modification in some types of biological neurons depends upon precise spike timing differences between presynaptic and postsynaptic spikes. Several temporally-asymmetric Hebbian learning rules motivated by this data have been proposed. We argue that such learning rules are suitable to analog VLSI implementation. We describe an easily tunable circuit to modify the weight of a silicon spiking neuron according to those learning rules. Test results from the fabrication of the circuit using a O.6J.lm CMOS process are given.


Citcuits for VLSI Implementation of Temporally Asymmetric Hebbian Learning

Neural Information Processing Systems

Experimental data has shown that synaptic strength modification in some types of biological neurons depends upon precise spike timing differences between presynaptic and postsynaptic spikes. Several temporally-asymmetric Hebbian learning rules motivated by this data have been proposed. We argue that such learning rules are suitable to analog VLSI implementation. We describe an easily tunable circuit to modify the weight of a silicon spiking neuron according to those learning rules. Test results from the fabrication of the circuit using a O.6J.lm CMOS process are given.


Citcuits for VLSI Implementation of Temporally Asymmetric Hebbian Learning

Neural Information Processing Systems

Experimental data has shown that synaptic strength modification in some types of biological neurons depends upon precise spike timing differencesbetween presynaptic and postsynaptic spikes. Several temporally-asymmetricHebbian learning rules motivated by this data have been proposed. We argue that such learning rules are suitable to analog VLSI implementation. We describe an easily tunablecircuit to modify the weight of a silicon spiking neuron according to those learning rules. Test results from the fabrication of the circuit using a O.6J.lm CMOS process are given.


Temporally Asymmetric Hebbian Learning, Spike liming and Neural Response Variability

Neural Information Processing Systems

Recent experimental data indicate that the strengthening or weakening of synaptic connections between neurons depends on the relative timing of pre-and postsynaptic action potentials. A Hebbian synaptic modification rule based on these data leads to a stable state in which the excitatory and inhibitory inputs to a neuron are balanced, producing an irregular pattern of firing. It has been proposed that neurons in vivo operate in such a mode.